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63.5 mmto inches

This thesis had finished 40×16 column interlaced dual-band infrared dual-band infrared focal plane array detectors. It was simulated using TSMC 0.35um Mixed Signal 2P4M CMOS 5V process. The pixel dimensions for two kinds of readout integrated circuits were also 30um×30μm. The test input current was set from 10nA to 25nA and the output swing was 2.1V to 3V, the pixel output rate was 6 MHz. The total power consumption was 16.2mW. In pixel readout circuit design, we used capacitor transimpedance amplifier (CTIA) readout circuit structure. CTIA is more advanced in noise rejection, gain control, dynamic range, uniformity and linearity. This thesis had designed 20×16 single-band capacitor transimpedance amplifier array readout circuit. It was also simulated using TSMC 0.35um Mixed Signal 2P4M CMOS 5V process. The pixel dimension was 30um×30μm. The simulation input current was set 0.01nA to 0.2nA, and the output swing was 0V to 2.78V. The pixel output rate was 6MHz and the total power consumption was 10.357mW. This thesis had also simulated capacitor transimpedance readout circuit for P-on-N or N-on-P two infrared sensor types. The pixel dimension was 30um×30μm. The input current was set 0.01nA to 1nA, the output swing was 1.2V to 2.8V, the pixel output rate was 6MHz for each wavelength. The total power consumption was 18.258mW. Key Words: CTIA, ROIC

本論文完成了40x16雙波段讀取電路之設計。此讀取電路採用了行交錯的讀取方式，採用了TSMC 0.35um 2P4M 5V的製程，中長波段像素電路的佈局面積各為30um x 30um。量測輸入電流設定在10nA~25nA，輸出電壓擺幅為2.1V~3V，像素輸出速率為12MHz，功率消耗為16.2mW。 在像素讀取電路的設計中，利用了電容式轉阻放大器的讀取電路的架構。電容式轉阻放大器擁有較好的抗雜訊功能、增益控制功能、動態範圍大，以及較好的線性度等優點。本論文設計了 20x16 單波段電容式轉阻放大器陣列讀取電路，採用了TSMC 0.35um 2P4M 5V的製程，像素電路的佈局面積為30um x 30um，模擬輸入電流設定在0.01nA~0.2nA，輸出電壓擺幅為0V~2.78V，像素輸出速率為6MHz，功率消耗為10.357mW。另外，以電容式轉阻放大器設計讀取電路適用於P-on-N或N-on-P類型紅外線感測器。像素電路的佈局面積為 30um x 30um，模擬輸入電流設定0.01nA~1nA，輸出電壓擺幅為1.2V~2.8V，各波段像素輸出速率為6MHz，功率消耗為18.258mW。 關鍵字:電容式轉阻放大器、紅外線讀取電路